ECE 274A
Digital Logic
Fall
Spring
Required Course:
Yes
Course Level
Undergraduate
Units
3
Prerequisite(s)
ECE 175. Prerequisite or concurrent enrollment in MATH 129.
Course Texts
Vahid, Frank. Digital Design. ZyBooks. Online.
Supplemental materials: Lysecky, Roman, and Frank Vahid. Verilog for Digital Design. ZyBooks. Online.
Schedule
150 minutes lecture, 170 minutes laboratory per week
Course Description
Number systems and coding, logic design, sequential systems, register transfer language.
Learning Outcomes
By the end of this course the student will be able to:
- Give precise definitions of a Boolean algebra, Boolean functions, implicants and prime implicants, and the SOP and POS canonical forms of representation
- Know how to construct basic gates (inverter, AND, OR) using NMOS and PMOS switches
- Know the cause of delays associated with logic gates
- Know number representations in different bases, and methods for converting from one base to another
- Know the different binary representations of signed integers (2s complement, 1s complement, sign magnitude), methods of conversion, and basic arithmetic operations (addition, subtraction, multiplication, division)
- Use Karnaugh maps and Quine-McCluskey tabular minimization technique for identifying all the prime implicants, and solve the covering problem to find a minimal gate, two-level implementation, for both completely specified and incompletely specified logic functions
- Understand the principles behind the heuristic methods for two level logic minimization
- Construct logic circuits of basic components such as adders, multipliers, decoders and multiplexors
- Have an understanding of programmable devices such as FPGAs, and know how to use them to implement digital circuits
- Have an understanding of the concept of state in functions that have history dependence
- Understand the structure and operation of basic flip flops and latches
- Know the structure and operation of ROMs and RAMs
- Define a finite state machine and know what functions can and cannot be described as finite state machines
- Be able to precisely define a Mealy and a Moore machine, and transform one to the other
- Know how to construct tabular and graph representations of finite state machines for an informal description, including state diagrams and state machine charts
- Have an understanding of the concept of machine equivalence, and be able to minimize a fully specified state table
- Be able to take an informal word description of a sequential process and synthesize a state machine that performs the function
- Know how to determine the clock period of a state machine
- Understand the principles of register-transfer level (RTL) design and high-level state machines
- Be able to take an informal word description of a digital circuit, design a high-level state machine for that circuit, and synthesize the high-level state machine to a final circuit implementation
- Be able to design circuits using Verilog
Course Topics
- Basic principles of digital logic
- Design, implementation and optimization of combinational circuits
- Classical, exact and heuristic optimization
- Design and implementation of sequential circuits
- Design of the basic subsystems of a microprocessor, such as registers, counters, memories, adders, multipliers and ALUs
- Register-transfer level (RTL) design of digital circuits
- Problem solving and design methodologies, including use of specific computer tools and simulations
- HDL programming using the Verilog language
Relationship to Student Outcomes
ECE 274A contributes directly to the following specific electrical and computer engineering student outcomes of the ECE department:
- Ability to design a system, component or process to meet desired needs within realistic constraints, such as economic, environmental, social, political, ethical, health and safety, manufacturability and sustainability (medium)
- Understanding of professional and ethical responsibility (low)
- Ability to use the techniques, skills and modern engineering tools necessary for engineering practice (high)
Syllabus Prepared By
Ratchaneekorn Thamvichai, 03/09/16