Computer-Aided Logic Design
There is no required textbook. The class is designed so that you do not have to purchase any textbooks. However, the lecture notes are based on the following textbooks:
- Cormen, Leiserson, Rivest, and Stein, Introduction to Algorithms, Third Edition, MIT Press.
- Frank Vahid and Roman Lysecky, Verilog for Digital Design, John Wiley & Sons.
- Frank Vahid, Digital Design, John Wiley & Sons.
- Robert K. Brayton, Gary D. Hatchel, C. McMullen, and Alberto L. Sangiovanni-Vincentelli, Logic Minimization Algorithms. for VLSI Synthesis, Kluwer Academic Publishers.
- Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill.
Specific Course Information:
2021-2022 Catalog Data: Tabular minimization of single and multiple output Boolean functions, NMOS and CMOS realizations, synthesis of sequential circuits, RTL description, laboratory exercises.
Specific Goals for the Course:
Outcomes of Instruction: By the end of this course the student will be able to:
- Understand the basics of high-level synthesis (HLS) and the benefits of HLS in improving productivity in the design of application-specific integrated circuits (or accelerators).
- Understand the importance of scheduling in HLS and learn how to use a variety of scheduling algorithms, including ASAP, ALAP, Hu, LIST_L, LIST_R, and force-directed.
- Understand a variety of methods used for resource sharing and binding.
- Understand the difference between heuristic and exact optimization methods, and be able to classify a variety of algorithms into these two categories.
- Use advanced techniques for logic minimization, including the Quine-McCluskey tabular minimization technique for identifying all the prime implicants, and solve the covering problem using Petrick’s method to find an optimal two-level implementation for specified logic functions.
- Use Quine-McCluskey with iterative and recursive consensus methods for identifying the complete sum and solve the covering problem using row/column dominance to find a minimal gate, two-level implementation for specified logic functions.
- Understand the role of verification in computer-aided design along with different testing methods.
- Design a simple high-level synthesis tool in C/C++ to output the resulting Verilog circuit implementation, given a behavioral netlist specification.
Brief list of topics to be covered:
- Hardware description languages (HDL)
- High-level synthesis (HLS): scheduling algorithms, resource sharing and binding, etc.
- Design and implementation of sequential circuits
- Register-transfer level (RTL) design
- Optimization and tradeoffs of combinational and sequential circuits
- Exact and heuristic minimization of two-level circuits
Relationship to Student Outcomes
ECE 474A contributes directly to the following specific electrical and computer engineering student outcomes of the ECE department:
1. An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics.
2. An ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors.