ECE Distinguished Seminar: Brad Burres
Friday, March 15, 2024 – 11:00 a.m.
Brad Burres
Intel Senior Fellow
Network and Edge Group
"Trends in the Cloud and at the Edge"
Health Science & Innovation Building (HSIB) Forum, Room 100B
The RSVP for lunch immediately following the seminar is now closed. We have reached capacity, but we hope you can join us for the seminar. If you have questions, please contact Keli Brinke, kelib@arizona.edu.
Join VIRTUALLY via Zoom
Abstract
This talk will address industry trends and domains Burres is working on including how CSPs are changing the compute platform with IPUs/DPUs, how AI training is impacting the network and how the era of Edge Computing is fast approaching.
Biography
Brad Burres is an Intel Senior Fellow and the Chief Hardware Architect for the Network and Edge Group (NEX). He is responsible for driving the technology and product definition for all of Intel’s foundational NICs and IPUs as well investing NEX's next-generation Edge SoCs.
Brad joined Intel in 1997 as a rotation engineer in Folsom, CA ending up in Hudson, MA as a key designer and architect on the IXP family of Network Processors. He spent several years on algorithms and accelerators before leading DPG into the System-On-a-Chip ecosystem. Brad was instrumental in creating and leading the Atom SoC line (Avoton/Rangeley, Denverton, Snow Ridge) and helped champion the creation of the Xeon-D line. He also led the Cedar Fork PCH – the first Atom and Xeon converged chipset. From there, he moved Intel into the SmartNIC/IPU domain. Brad’s work has led to more than 50 patents, 25 pending patents, one Intel Achievement Award and many industry conference presentations.
Brad received his BS in computer engineering from The University of Arizona and his MS in electrical engineering from Worcester Polytechnic Institute.