Jump to navigation

The University of Arizona Wordmark Line Logo White
College of Engineering
Home
  • Home
  • Give Today
  • Contact Us

Search form

  • About
    • Welcome
    • Advisory Board
    • Contact Us
  • Undergrad Programs
    • Admissions
    • Degrees
    • Courses
    • Advising
    • Scholarships & Financial Aid
    • Research & Internships
    • Student Clubs & Organizations
    • ABET Accreditation
  • Grad Programs
    • Admissions
    • On-Campus Degrees
    • Online Degrees
    • Courses
    • Advising
    • Research Focus Areas
    • Funding
  • Research
    • Focus Areas
    • Centers
    • Inventions
  • Faculty & Staff
    • Faculty Directory
    • Staff Directory
    • Faculty Videos
    • Employee Resources
    • Open Positions
  • Alumni
    • Give Today
  • News & Events
    • ECE News Archive
    • Events
Graduate Programs
Home / Graduate Programs / Courses / Computer-Aided Logic Design

ECE 574A

Computer-Aided Logic Design

Fall
Required Course:
Yes

Course Level

Graduate

Units

3

Prerequisite(s)

ECE 275

Course Texts

No textbook is required. The class notes and slides are sourced from the following materials:

  • Digital Design, Frank Vahid, John Wiley & Sons, ISBN 0470044373
  • Verilog for Digital Design, Frank Vahid and Roman Lysecky, John Wiley & Sons, ISBN 9780470052624
  • Logic Synthesis and Verification Algorithms, Gary D. Hachtel and Fabio Somenzi, Springer, ISBN 0387310045
  • Logic Minimization Algorithms for VLSI Synthesis, Robert K. Brayton, Gary D. Hathtel, C. McMullen, and Alberto L. Sangiovanni-Vincentelli, Kluwer Academic Publishers, ISBN 0898381649
  • Introduction to Algorithms, Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest, McGraw-Hill, 0070131430
  • Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, ISBN 0070163332

Schedule

150 minutes lecture per week

Course Links

ECE 474A/574A Course Website

Course Description

This course is an introduction to computer-aided logic design. This is a highly active research area, enabling the design of increasingly complex digital systems. In this course we will mainly focus on three areas: specification, synthesis and optimization. We will look at how to specify functionality at a variety of abstractions, use industry-standard tools to simulate these designs, investigate some of the underlying optimization techniques utilized, as well as develop your own tools. Topics include, but are not limited to: 1) Register-Transfer Level, or RTL, Design, 2) Behavioral Synthesis, 3) Optimization and Tradeoffs of Combinational and Sequential Circuits, 4) Exact and Heuristic Minimization of Two-Level Circuits.

Students will be expected to implement a variety of Verilog and C/C++ projects throughout the semester. While specific programming assignments may change with the course offering, projects typically focus on the implementation of optimization and synthesis methods discussed in class, as well as the RTL design. 

Assessment

  • Exam: 4 (lowest score dropped)
  • Project: 4 programming projects
  • Participation: 12-15 participation activities (1 dropped)
  • Typical grading policy: 55% exams, 40% programming assignments, 5% participation/in-class exercises

Syllabus Prepared By

Susan Lysecky, April 2013
  • GRAD PROGRAMS
  • Admissions
  • On-Campus Degrees
  • Online Degrees
  • Courses
  • Advising
  • Research Focus Areas
  • Funding
gradadvisor@ece.arizona.edu
  • Cadence University Program Member
  • Employee Resources
The University of Arizona
Department of Electrical & Computer Engineering
1230 E. Speedway Blvd.
P.O. Box 210104
Tucson, AZ 85721-0104
520.621.6193

Facebook YouTube LinkedIn


University Privacy Statement

© 2022 The Arizona Board of Regents on behalf of The University of Arizona.