Professor of Electrical and Computer Engineering
Professor of Mathematics
Professor, Applied Mathematics - GIDP
Professor, BIO5 Institute
Bane Vasić is a professor of electrical and computer engineering and mathematics at the University of Arizona and a director of the Error Correction Laboratory. He is one of the inventors of the soft error-event decoding algorithm, and the key architect of a detector/decoder for Bell Labs' data storage read-channel chips regarded as the best in industry.
His pioneering work on structured low-density parity check (LDPC) error correcting codes based on combinatorial designs has enabled low-complexity iterative decoder implementations. Structured LDPC codes are today adopted in a number of communications standards and data storage systems and are a prime candidate for quantum error correction. Dr. Vasić’ work on codes on graphs, trapping sets and error floor of iterative decoding algorithms has led to decoders for the binary symmetric channel with best error-floor performance known today.
He is a founder of Codelucida, a company developing advanced error correction solutions for flash memories. He is an IEEE Fellow, Fulbright Scholar, da Vinci Fellow, and a past Chair of IEEE Data Storage Technical Committee.
- PhD: electrical engineering, University of Nis, Serbia, 1994
- MS: electrical engineering, University of Nis, Serbia, 1991
- BS: electrical engineering, University of Nis, Serbia, 1989
Undergraduate engineering systems analysis; graduate error correction codes, probability and random processes, and digital communications systems
Coding theory, information theory, digital communications, and memory and storage systems
Textbooks/Most Significant Publications
N. Raveendran, D. Declercq, and B. Vasić, "A Sub-Graph Expansion-Contraction Method for Error Floor Computation," IEEE Transactions on Communications, 2020.
B. Vasić and P. Ivaniš, "Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media," IEEE Transactions on Communications, 2016.
D. V. Nguyen and B. Vasić, "Two-Bit Bit Flipping Algorithms for LDPC Codes and Collective Error Correction," IEEE Transactions on Communications, 2014.
S. K. Planjery, D. Declercq, L. Danjean, and B. Vasić, "Finite Alphabet Iterative Decoders, Part I: Decoding Beyond Belief Propagation on the Binary Symmetric Channel," IEEE Transactions on Communications, 2013.
S. K. Chilappagari, D. V. Nguyen, B. Vasić, and M. W. Marcellin, "On Trapping Sets and Guaranteed Error Correction Capability of LDPC codes and GLDPC Codes," IEEE Transactions on Information Theory, 2010.
S. K. Chilappagari and B. Vasić, "Error-Correction Capability of Column-Weight-Three LDPC Codes," IEEE Transactions on Information Theory, 2008.
B. Vasić and S. K. Chilappagari, "An information theoretical framework for analysis and design of nano-scale fault-tolerant memories based on low-density parity-check codes," IEEE Transactions on Circuits and Systems, 2007.
B. Vasić and O. Milenković, "Combinatorial constructions of low-density parity-check codes for iterative decoding," IEEE Transactions on Information Theory, 2004.