Bane Vasić

Bane Vasić is a professor of electrical and computer engineering and mathematics at the University of Arizona and a director of the Error Correction Laboratory. He is an inventor of the soft error-event decoding algorithm for inter symbol interference channels with correlated noise, and the key architect of a detector/decoder for Bell Labs data storage read channel chips which were regarded as the best in industry. His pioneering work on structured low-density parity check (LDPC) error correcting codes based on combinatorial designs has enabled low-complexity iterative decoder implementations. Structured LDPC codes are today adopted in a number of communications standards and data storage systems. Vasic’s work on codes on graphs, trapping sets and error floor of iterative decoding algorithms has led to decoders for the binary symmetric channel with best error-floor performance known today. He is a co-PI on a Department of Energy multi-university $115M-project led by Fermi National Laboratory to establish a Center for Superconducting Materials and Systems. He is a co-PI of the $52M NSF Center for Quantum Network hosted at the University of Arizona. He is also funded by NASA-Jet Propulsion Laboratory through the Strategic University Partnership Program for the development of quantum codes and error correction algorithms for NASA space missions and is a PI on seven research grants funded by the National Science Foundation. Vasic is an IEEE Fellow, Fulbright Scholar, da Vinci Fellow and a past Chair of IEEE Data Storage Technical Committee.

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